Interleaved ADC: Analysis of Accuracy and Methods for Improving It

As modern communication transceivers scale to multi-Gbps speeds, the power consumption and cost of highresolution, high-speed analog-to-digital converters (ADCs) become a crucial bottleneck in realizing “mostly digital” receiver architectures that leverage Moore's law. This bottleneck could potentially be alleviated by designing analog front ends for the more specific goal of analog-to-information conversion (i.e., preserving the digital information residing in the received signal). As one possible approach towards this goal, we consider a generalization of the standard flash ADC: instead of implementing n bit quantization of a sample by passing it through 2 n -1 slicers as in a standard ADC, the slicers are dispersed in time as well as space (i.e., amplitude). Considering BPSK over a dispersive channel, we first show, using ideas similar to those underlying compressive sensing, that randomly dispersing enough one-bit slicers over space and time does provide information sufficient for reliable demodulation over a dispersive channel. We then propose an iterative algorithm for optimizing the design of the sampling times and amplitude thresholds, and provide numerical results showing that the number of slicers can be significantly reduced relative to a conventional flash ADC with comparable bit error rate (BER). These system-level results motivate further investigation, in terms of both circuit and system design, into looking beyond conventional ADC architectures when designing analog front-ends for high-speed communication.

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

The need for low-power wireless sensor networks (WSNs) continues to grow. Based on the fact that digital-to-analog converters (DACs) are essential elements in the WSN and consumes a lot of power, this paper presents a new low-power DAC design to realize the low-power WSN. To do that, this paper exploits the dynamic element matching (DEM) technique, one of the well-known techniques for high performance DACs, proposes a lightweight DEM (LW-DEM) technique that minimizes power and area overhead of the DEM technique. More specifically, this paper is motivated from the observation that input data of DACs tends to be sufficiently random that the input data can be used for the random selection of the current source instead of a pseudo-random number generator (PRNG) for the traditional DEM. Because the PRNG consumes a lot of power and occupies a large area in a DAC, elimination of the PRNG from a DAC and utilizing input data result in significant power saving and area reduction in the DAC while meeting the required performance of the low-power WSNs. This paper provides a detailed LW-DEM architecture and its operation principle. To demonstrate the efficacy of the proposed method, a prototype 12-bit DAC using the LW-DEM is implemented. The 12-bit DAC is fabricated in 65 nm CMOS technology and occupies only $0.065~{mm}^{2}$ area. Measurement results with the prototype verify that the DAC using LW-DEM accomplishes 39% power saving and 52% area reduction in the randomizer, compared to a DAC using the conventional DEM. At the same time, the measured spurious-free dynamic range (SFDR) of the DAC using LW-DEM is better than 55 dB, demonstrating that the proposed DAC achieves almost same performance as a DAC using the conventional DEM.

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

This architecture is designed for wireless body sensor networks (WBSN). Depend on the signal under concerned system should change its sampling frequency that is when the amplitude of a signal suddenly varies more than the step size of the Analog to Digital Converter (ADC). An adaptive system is employed to detect the change in amplitude and depending on its output frequency selector circuit selects sampling frequency of ADC. For data acquisition the Successive Approximation Register (SAR) ADC is the best choice. It works on low power, Medium frequency, and high resolution. In this paper, a system is designed in 45nm technology and simulated in Cadence Virtuoso Environment. Its maximum working Frequency is 5 MHz and consumes 1.47mW of Power.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

There is a huge increase in data in terms of data conversion that effects the performance and complexity of the devices like analog-to-digital converters (ADC).The standard ADC uses the conventional Shannon-Nyquist Theorem which says that sampling frequency should be twice of the maximum frequency. These samples require very huge storage.Compressive sensing(CS) which gives solution to this problem. In CS we decrease the sampling rate much less than the Nyquist rate and reconstruct the original signal.There are different reconstruction algorithms evolved since from its origin each. In this paper, we are making a comparison between the performances of Orthogonal Matching Pursuit(OMP) and Regularised Orthogonal Matching Pursuit(ROMP) algorithms for image reconstruction.

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line.In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

This paper presents a novel technique for digital to analog conversion, which uses flash transistors embedded in a traditional current-steering digital to analog converter (DAC) architecture. Our design utilizes flash transistors as programmable, tunable current sources. Our DAC achieves extremely low latency, area, and power, making it especially suited for the internet of things (IoT) and other applications with a highly constrained resource budget. In addition, the use of flash transistors allows a user to cancel errors due to process/voltage variations and chip aging. This tuning can be performed in the fabrication facility, or in-field. We perform a Monte-Carlo analysis to demonstrate the performance of our DAC in a real-world context. Compared to recent DACs intended for use in IoT devices (or for applications that are highly resource constrained), we significantly improve error metrics. We reduce chip area by 4.3× compared with the smallest DAC intended for IoT. Additionally, we improve throughput by 55 ×and energy per conversion by 33×, compared with the fastest and the most energy efficient DAC intended for IoT, respectively. The proposed 12-bit DAC achieves a throughput of 100 MS/s, an energy per conversion of 36.6 fJ. Based on Monte Carlo analysis, we report a maximum INL (DNL) of 1.242 LSB (0.757 LSB), an average INL (DNL) of 0.286 LSB (0.088 LSB), an ENOB of 11.80 bits, and an SFDR of 82.89 dB.

Partial discharge (PD) diagnostic on high voltage (HV) power cables is a modern technology in order to investigate the insulation health. The trending technology such as wireless sensor network (WSN) and internet of thing (IoT) are mostly process in digital signal by microprocessor where looking toward on automatic system. The high performance of analog to digital converter (ADC) in term of sampling rate which is much expensive in order to convert the high frequency of analog PD signal that captured by Rogowski coil (RC) sensor. Thus, this paper propose the implementation of the Sigma-Delta (∑Δ) ADC topology in Altera DE0-Nano development board as an effective method in this work to replace the conventional ADC chip and the cost is minimal. Then, peak PD detection technique is applied after the conversion of the digital PD signal. The Verilog hardware description language (VHDL) is used in Quartus II software which corporate with Altera DE0-nano development board for the prototype development. In order to achieve the accurate digital sampling of high frequency PD signal, the N-bit of voltage resolution is paramount.

Stochastic flash analog-to-digital converters (ADCs) have been proposed as a solution to the scalability problems encountered by a standard flash ADC. Instead of generating comparator references with a well-matched resistor ladder, it generates randomly distributed thresholds using either the comparator offsets or a separate noise-generating circuit. This allows all devices to be minimum size without matching problems; consequently the stochastic ADC becomes an attractive solution for a synthesizable ADC design. This work achieves two goals: first, it derives the relationship between the number of comparator decisions and effective resolution of a stochastic ADC with an arbitrary probability distribution function (PDF) of comparator thresholds. Second, this work identifies the conditions under which linearity calibration will improve performance. Monte-Carlo simulations demonstrate that for high signal amplitude or numbers of comparisons, calibration significantly improves resolution. For low amplitudes or numbers of comparisons, the ADC performs better without linearity calibration.

Wireless Sensor Network (WSN) for environmental monitoring in a form of a sensor platform is built with individual nodes, called sensors, that accepts analog signals detected from the changes of state in the environment. One of the crucial parts of a WSN is an Analog-to-Digital Converter (ADC) which acts as the interface between the environment and the platform. Since the WSN is for environmental monitoring, it is powered by an energy harvesting unit which demands for low-energy consumption on the constituent blocks including the ADC. Implementing a high-resolution converter can mean higher energy consumption and a much accurate digital result, nonetheless, lower resolution converter consumes less energy but still can give correct digital output. This trade-off between accuracy and energy consumption made impact to the researchers to develop a programmable Successive Approximation Register ADC for WSN. This research study was implemented using Synopsys EDA Tool in 90nm CMOS Process Technology. The SAR ADC was successfully designed with 8-bits and 14-bits resolution, a sampling rate of 100ksps and 62.5ksps, respectively. The energy consumption of the SAR ADC is 234pJ (8-bits) and 366.72pJ (14-bits), and an energy saving of 36.2%.

The effects of analog-to-digital conversion (ADC) quantization noise on the recovery of harmonic amplitudes and phases in the presence of large fundamental amplitudes are examined by theory and simulation, in order to determine the noise limits of instrumentation system design for power systems monitoring and harmonic power-flow measurement. Amplitude and phase errors are independent of the harmonic order; the amplitude error is independent of harmonic amplitude for sufficiently large signal-to-noise ratios; and the phase error is inversely proportional to harmonic amplitude. The noises may be reduced by increasing the ADC width or the transform length. Graphs are presented which show the various tradeoffs which can be made, in particular, between harmonic phase recovery and ADC width