Interface Engineering by PVD-Based In-Situ Fabrication Method for Advanced Metal/High-k Gate Stacks

Abstract

We fabricated high-quality silicate gate dielectrics by utilizing a solid phase interface reaction (SPIR) between ultrathin metal layers and SiO2 underlayers. Metal diffusion to the SiO2 underlayer forms a high-quality silicate interlayer, and preserving the initial SiO2/Si bottom interface ensures good electrical properties. The Hf silicate dielectrics were fabricated by the SPIR method using Hf layers less than 0.5-nm-thick that were fully consumed by interface reactions, resulting in Hf silicate layers that remained amorphous after activation annealing. The superior electrical properties of the poly-Si/HfSixOy/SiO2/Si MOSFETs were demonstrated through low leakage current and high electron mobility. We also recently proposed a novel in-situ fabrication method that continuously fabricates high-k dielectrics using SPIR and metal electrodes with a low-damage sputtering system. We investigated structural and electrical properties of metal/high-k gate stacks and demonstrated the effectiveness of the in-situ method in improving electrical properties.