Inter-Chip Authentication through I/O Character

Abstract

Providing resistance against hardware attacks is important to ensure trusted or secure computing. Approach of inter-chip authentication is proposed, which can be applied to detect malicious tamper to chips/components equipped on the circuit board. The proposed approach is to utilize the I/O physical timing characters to obtain a specified fingerprint for each specified chip on the board, and to check the validity of the chip by matching its fingerprint for later usage. To obtain the required fingerprint, an inner sampling logic is set after the I/O pins to get the timing characters reflected on the lines connected between the master chip and the slave chip to be verified. From the sampling result, the physical character associated with the slave chip is extracted and compared with the valid one. Because tampers will influence the physical character to distort the fingerprint, it has the abilities to detect tamper behaviors like chip replacement and faked signal injection. A logic analyzer and 8051-MCU based evaluation system is constructed. The test result shows that it can effectively identify the valid chip from the faked ones. Hence, the proposed approach can be deployed into the circuit board to protect the chips equipped on the board against hardware attacks.