Abstract
Interleaving is a powerful technique that boosts the speed of an ADC. The power efficiency of such a technique is mainly affected by the overhead of the circuitry used to mitigate the impact of inter-channel mismatches on the ADC’s performance. This paper reviews some of the most important methods of calibrating such mismatches and presents a frequency-domain analysis of timing skew in a time-interleaved (TI) ADC. A new calibration approach is also proposed that calibrates the timing and offset mismatches between the channels simultaneously. Behavioral modeling simulations of a 15-channel 10-b 2GS/s TI SAR ADC show an improvement of 35 dB in the SFDR after calibration. The impact of circuit nonidealities and noise is also assessed, and mitigation techniques are proposed.
Highlights
T IME interleaving is a technique that allows multiple identical analog-to-digital converters (ADCs) to operate in parallel and process the input at a faster rate than the operating speed of each individual converter
If M channels1 operate in parallel, the overall ADC’s speed increases by a factor M compared to the speed of a single sub-ADC
Throughout this article, M, N, fs, Ts and fin denote the number of channels of the TI ADC, the resolution, the sampling frequency, the sampling period and the maximum input frequency, respectively
Summary
T IME interleaving is a technique that allows multiple identical analog-to-digital converters (ADCs) to operate in parallel and process the input at a faster rate than the operating speed of each individual converter. The maximum realistic speed of the sub-ADCs is a limiting factor to the maximum achievable speed of the timeinterleaved (TI) ADC. Where P is the power consumption, ENOB is the effective number of bits and fs is the Nyquist-rate sampling frequency, is typically used to report on the energy efficiency of an ADC. As long as the power consumption of a sub-ADC scales linearly with the sampling speed, the equivalent time-interleaved ADC will always be less energy-efficient than its constituent sub-ADCs because of the overhead associated with interleaving, e.g., the multiphase clock generation and distribution and the correction of interchannel mismatches [1].
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