Inter multi processor communication scheme and shared memory control in the HDTV decoder SOC design

Abstract

With the improvement of integration degree, more and more systems that originally implemented on PCB board are integrated into one chip, becoming a SOC (system on a chip). Also with the increasing demand for programmable performance, the use of multi microprocessors structure in SOC designs is becoming much more popular. For the complex real-time systems such as HDTV decoder, it is generally easier with multiple CPUs to provide instant response time and meet the demand of real-time and function complexity. In this paper, based on introduction of the HDTV SOC architecture we designed, a communication and control scheme between master-slave mode dual-processors in the SOC is proposed, as well as a shared memory control method among multi IP function modules in the SOC.