Intelligent optical backplanes

Abstract

One of the practical limiting factors in the development and acceptance of teraflop multiprocessor computing systems (as well as large ATM switching systems) is packaging. Currently large systems, 64 processing nodes and above, can require multiple cabinets to house all their electronic equipment. This low-density packaging not only leads to expensive systems but also suffers from increased latency, skew, and other physical problems that limit overall performance. As thermal management schemes have progressed there is a growing trend to package more electronics into smaller physical volumes. The result is the integration of more processing nodes (PN) per integrated circuit, more PNs per printed circuit board (PCB), and more PCBs per shelf. This necessary hardware compression leads to an interconnect bottleneck at the backplane. One approach to overcome these interconnection limitations of electrical backplanes is to exploit the temporal and spatial bandwidth available with the free-space optical technology. A free-space optical backplane is composed of a large number of optically interconnected smart pixel arrays (SPAs). A smart pixel is an optoelectronic device that combines optical inputs and/or outputs with electronic processing circuitry, and is capable of being integrated into two-dimensional arrays. In an intelligent optical backplane, the SPAs control the flow of information between the PCBs.