Abstract
In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation which iteratively applies behavioral synthesis and floorplanning to obtain an optimum circuit in terms of performance under given design constraints. We evaluate the effectiveness of the proposed method through synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to ones without considering timing constraints. Also, the proposed method is effective to reduce the number of timing violations.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
