Integration of a W-plug in an Al-based metallization scheme for 0.25-μm IC technology

Abstract

Tight interconnect design rules associated with 0.25 micrometer technology and below introduces a number of challenges in backend integration in the course of developing an appropriate process architecture. In this paper, the effect of the underlying metallization on via electrical performance and the attendant integration issues are discussed. For a Ti/TiN/Al-based metal stack, increasing the TiN cap thickness was found to significantly reduce via resistance. Since high density plasma CVD is commonly used to deposit gap-fill oxide after metal patterning, the effect on via resistance of oxygen plasma exposure of the underlying metal stack was also evaluated. A layer of Ti sandwiched between Al and cap TiN was found to give consistently low via resistance values due to reduction of the interfacial resistance contribution from the via/bottom metal interface. In some cases, where W remained exposed after dry etching of the subsequent metal level, complete corrosion of W was observed during solvent strip, for certain structures. Based on these results, various via integration options for current and future multilevel metal interconnect architecture are considered.