Integrated on-chip storage evaluation in ASIP synthesis

Abstract

An application specific instruction set processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements. Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by approaches which perform only scheduling for performance estimation and avoid code generation. However, existing scheduler based approaches do not help in exploring on-chip storage organization. We present a scheduler based technique for exploring the register file size, number of register windows and cache configurations in an integrated manner. Performance for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. Number of context switches leading to spills are estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance.