Integrated CMOS ADC — Tutorial review on recent hybrid SAR-ADCs

Abstract

Recently, SAR-ADC architecture is often used as an integrated ADC architecture in VLSI chip. The advantage of SAR ADC is the non-necessity of high-gain OP amps, low power consumption features, and it's suitability to fine process. On the other hand, disadvantage with simple SAR architecture, however, is its difficulty to achieve high-sampling frequency and/or high SNDR. There are many proposals on SAR ADC operation speed improvement. Apart from time-interleaving, pipelined SAR approach helps to speed up the A/D conversion. Also, many precision improvement methods are proposed. Among these, hybrid architecture such as combination of SAR and oversampling or noise-shaping is useful to improve SNDR of the ADCs. This tutorial reviews recent progress on CMOS hybrid ADC architectures with high speed and/or high SNDR hybrid ADCs.