Abstract
A novel characterization methodology for integrated capacitor array mismatch determination is presented. The circuit allows multiplexed biasing of 20 capacitor units and the selection of a specific array on chip. Information about the spatial matching behavior is provided for an entire poly-Si capacitor array, where the relevant parameters are the standard deviations σ(ΔC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> /C) and the offsets μ(ΔC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> /C) of units i. The circuit design and the measurement strategy are discussed in detail. Furthermore, the measurement reproducibility is determined quantitatively and correlations introduced by the extraction method are investigated. The corresponding test chips were successfully realized in 0.35- and 0.18-μm standard CMOS technologies. Results for the poly-Si capacitor array (0.35-μm technology) are presented in this paper.
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