Abstract
In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I & F neuron circuit, the basic I & F and synaptic off-current blocking operations of the proposed I & F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I & F neuron circuits. The simulation and analysis results demonstrate the robustness of the I & F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices.
Highlights
Various attempts have been made on neuromorphic computing systems to emulate biological brain behavior in terms of energy consumption and parallel processing [1]–[4]
Compared to the von Neumann architecture, a neuromorphic computing system based on a spiking neural network (SNN) is suitable for complex data processing such as pattern recognition [5], [6], image denoising [7], and speech recognition [8] owing to the energy efficiency and parallel processing capability of SNNs
Synaptic devices made of field effect transistors (FETs) or memristors have off-state current components even when no input spike is applied [29]–[31], which may vary depending on the synaptic weights
Summary
Various attempts have been made on neuromorphic computing systems to emulate biological brain behavior in terms of energy consumption and parallel processing [1]–[4]. The firing rate of the I & F neuron circuit and the common output activation function of the non-spiking ANN, rectified linear unit, perform the same function when there is no extra current component of the synapse. Recent studies on silicon neuron circuits [16], [17], [22], [24], [28] and non-silicon materials [18]–[20] exhibit extremely low energy consumption, but their firing rate can still be affected by the synaptic off-current, which is an external off-current component of the neuron circuit. The leaky I & F neuron circuit has its limitations in multi-layer SNNs in terms of blocking the synaptic off-current, even if the off-current in each synaptic device is not weight-dependent. We propose a novel method to minimize the effect of the synaptic off-current on SNN inference systems, irrespective of the device or array type.
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