Innovative Thermal Approaches to Fault Isolation in Three-Dimensional Semiconductor Structures

Compared to planar NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. Our goal is to (1)~identify and understand these new error characteristics of 3D NAND flash memory, and (2)~develop new techniques to mitigate prevailing 3D NAND flash errors. \chIIIn this paper, we perform a rigorous experimental characterization of real, state-of-the-art 3D NAND flash memory chips, and identify three new error characteristics that were not previously observed in planar NAND flash memory, but are fundamental to the new architecture of 3D NAND flash memory. \beginenumerate [leftmargin=13pt] ıtem 3D NAND flash memory exhibits layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different. We are the first to provide detailed experimental characterization results of layer-to-layer process variation in real flash devices in open literature. Our results show that the raw bit error rate in the middle layer can be 6× the error rate in the top layer. ıtem 3D NAND flash memory experiences \emphearly retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming, but then increases at a much slower rate. We are the first to perform an extended-duration observation of early retention loss over the course of 24~days. Our results show that the retention error rate in a 3D NAND flash memory block quickly increases by an order of magnitude within $\sim$3 hours after programming. ıtem 3D NAND flash memory experiences retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells. Our results show that charge leaks at a lower rate (i.e., the retention loss speed is slower) when the neighboring cell is in a state that holds more charge (i.e., a higher-voltage state). \endenumerate Our experimental observations indicate that we must revisit the error models and error mitigation mechanisms devised for planar NAND flash, as they are no longer accurate for 3D NAND flash behavior. To this end, we develop \emphnew analytical model\chIs of (1)~the layer-to-layer process variation in 3D NAND flash memory, and (2)~retention loss in 3D NAND flash memory. Our models estimate the raw bit error rate (RBER), threshold voltage distribution, and the \emphoptimal read reference voltage (i.e., the voltage at which RBER is minimized when applied during a read operation) for each flash page. Both models are useful for developing techniques to mitigate raw bit errors in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, LaVAR, reduces process variation by fine-tuning the read reference voltage independently for each layer. Our second technique, LI-RAID, improves reliability by changing how pages are grouped under the RAID (Redundant Array of Independent Disks) error recovery technique, using information about layer-to-layer process variation to reduce the likelihood that the RAID recovery of a group could fail significantly earlier during the flash lifetime than recovery of other groups. Our third technique, ReMAR, reduces retention errors in 3D NAND flash memory by tracking the retention age of the data using our retention model and adapting the read reference voltage to data age. Our fourth technique, ReNAC, adapts the read reference voltage to the amount of retention interference to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash manufacturer wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%. For more information on our new experimental characterization of modern 3D NAND flash memory chips and our proposed models and techniques, please refer to the full version of our paper~\citeluo.pomacs18.

Compared to planar NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. Our goal is to (1)~identify and understand these new error characteristics of 3D NAND flash memory, and (2)~develop new techniques to mitigate prevailing 3D NAND flash errors. \chIIIn this paper, we perform a rigorous experimental characterization of real, state-of-the-art 3D NAND flash memory chips, and identify three new error characteristics that were not previously observed in planar NAND flash memory, but are fundamental to the new architecture of 3D NAND flash memory. \beginenumerate [leftmargin=13pt] ıtem 3D NAND flash memory exhibits layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different. We are the first to provide detailed experimental characterization results of layer-to-layer process variation in real flash devices in open literature. Our results show that the raw bit error rate in the middle layer can be 6× the error rate in the top layer. ıtem 3D NAND flash memory experiences \emphearly retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming, but then increases at a much slower rate. We are the first to perform an extended-duration observation of early retention loss over the course of 24~days. Our results show that the retention error rate in a 3D NAND flash memory block quickly increases by an order of magnitude within $\sim$3 hours after programming. ıtem 3D NAND flash memory experiences retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells. Our results show that charge leaks at a lower rate (i.e., the retention loss speed is slower) when the neighboring cell is in a state that holds more charge (i.e., a higher-voltage state). \endenumerate Our experimental observations indicate that we must revisit the error models and error mitigation mechanisms devised for planar NAND flash, as they are no longer accurate for 3D NAND flash behavior. To this end, we develop \emphnew analytical model\chIs of (1)~the layer-to-layer process variation in 3D NAND flash memory, and (2)~retention loss in 3D NAND flash memory. Our models estimate the raw bit error rate (RBER), threshold voltage distribution, and the \emphoptimal read reference voltage (i.e., the voltage at which RBER is minimized when applied during a read operation) for each flash page. Both models are useful for developing techniques to mitigate raw bit errors in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, LaVAR, reduces process variation by fine-tuning the read reference voltage independently for each layer. Our second technique, LI-RAID, improves reliability by changing how pages are grouped under the RAID (Redundant Array of Independent Disks) error recovery technique, using information about layer-to-layer process variation to reduce the likelihood that the RAID recovery of a group could fail significantly earlier during the flash lifetime than recovery of other groups. Our third technique, ReMAR, reduces retention errors in 3D NAND flash memory by tracking the retention age of the data using our retention model and adapting the read reference voltage to data age. Our fourth technique, ReNAC, adapts the read reference voltage to the amount of retention interference to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash manufacturer wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%. For more information on our new experimental characterization of modern 3D NAND flash memory chips and our proposed models and techniques, please refer to the full version of our paper~\citeluo.pomacs18.

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell. Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

Secure edge devices and the need for hardware security are of paramount importance due to the growing demand for cybersecurity. Hardware security has been strengthened using complex architecture to provide uncompromisable security and prevent malicious cybersecurity attacks. To prevent unauthorized access using even the most advanced failure analysis (FA) techniques, the Hardware Security Module (HSM) implements cryptographic algorithms and data obfuscation using many raw combinational logic and state machines. When a newly taped-out device fails to operate or fails to come out of its secure boot-up sequence, how can we know whether a defect is present or if the security block reacted to a design error? This paper discusses various real-world examples of FA challenges related to first silicon debug, including secure IP. We explore the unique approaches required to make sense of collected Laser Voltage Probe (LVP), Photon Emission Microscopy (PEM), and Laser Logic State Mapping (LLSM) data. We discuss some of the most advanced FA techniques' strengths and weaknesses and illustrate how system architecture related to securing data can be modified to alter the effectiveness of each. We explain in detail why specific FA techniques can be defeated by built-in security and where FA techniques can be enabled by clever triggering schemes or looping on areas of code while looking for specific behaviors. This paper also talks about the limitations of analyzing complex architecture being good from a security point of view. We conclude by summarizing the threat FA tools present to secure IP and comment on steps that could be taken to further protect internal state machines and sensitive logic areas from even the most well-equipped FA labs. Thus, this work gives an introspective thought as to how Optical Fault Isolation (OFI) techniques could be perceived as a threat to various security applications and points to trade-offs between the ability to analyze versus hardware security.

As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the computing in a memory chip, a new candidate with high density and a large on/off current ratio is now urgently needed. Here, we first report that 3D NAND flash memory with a high density of multilevel storage can be realized in a double-layered Si quantum dot floating-gate MOS structure. The largest capacitance–voltage (C-V) memory window of 6.6 V is twice as much as that of the device with single-layer nc-Si quantum dots. Furthermore, the stable memory window of 5.5 V can be kept after the retention time of 105 s. The obvious conductance–voltage (G-V) peaks related to the charging process can be observed, which further confirms that the multilevel storage can be realized in double-layer Si quantum dots. Moreover, the on/off ratio of 3D NAND flash memory with a nc-Si floating gate can reach 104, displaying the characteristic of a depletion working mode of an N-type channel. The memory window of 3 V can be maintained after 105 P/E cycles. The programming and erasing speed can arrive at 100 µs under the bias of +7 V and −7 V. Our introduction of double-layer Si quantum dots in 3D NAND float gating memory supplies a new way to the realization of computing in memory.

NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory. Recently, 3-dimensional (3D) NAND flash memory was developed and started mass-production for reducing bit cost. By using 3D NAND flash memory, an advanced SSD has been intensively developed for high performance, and low power consumption, namely ecological environment. In this paper, NAND Flash memory technologies are discussed in the past, present and future.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

Compression has been demonstrated as an efficient method for lifetime improvement on flash memory. However, data compression ratios are various, which bring proportional wearing on flash pages. Furthermore, the compression schemes have still not been considered in the design of the state-of-the-art wear leveling schemes. Thus, there will be some waste on lifetime exploitation, especially for three-dimensional (3D) NAND flash memory. 3D NAND flash memory is developed to boost the storage capacity by stacking memory cells vertically. However, in 3D NAND flash, one critical characteristic is that its endurance is significantly varied from blocks to pages. Thus, it is necessary to revisit the wear leveling mechanism for compression applied 3D NAND flash memory for further lifetime improvement.

NAND flash memory density continues to scale to keep up with the increasing storage demands of data-intensive applications. Unfortunately, as a result of this scaling, the lifetime of NAND flash memory has been decreasing. Each cell in NAND flash memory can endure only a limited number of writes, due to the damage caused by each program and erase operation on the cell. This damage can be partially repaired on its own during the idle time between program or erase operations (known as the dwell time), via a phenomenon known as the self-recovery effect. Prior works study the self-recovery effect for planar (i.e., 2D) NAND flash memory, and propose to exploit it to improve flash lifetime, by applying high temperature to accelerate self-recovery. However, these findings may not be directly applicable to 3D NAND flash memory, due to significant changes in the design and manufacturing process that are required to enable practical 3D stacking for NAND flash memory. In this paper, we perform the first detailed experimental characterization of the effects of self-recovery and temperature on real, state-of-the-art 3D NAND flash memory devices. We show that these effects influence two major factors of NAND flash memory reliability: (1) retention loss speed (i.e., the speed at which a flash cell leaks charge), and (2) program variation (i.e., the difference in programming speed across flash cells). We find that self-recovery and temperature affect 3D NAND flash memory quite differently than they affect planar NAND flash memory, rendering prior models of self-recovery and temperature ineffective for 3D NAND flash memory. Using our characterization results, we develop a new model for 3D NAND flash memory reliability, which predicts how retention, wearout, self-recovery, and temperature affect raw bit error rates and cell threshold voltages. We show that our model is accurate, with an error of only 4.9%. Based on our experimental findings and our model, we propose HeatWatch, a new mechanism to improve 3D NAND flash memory reliability. The key idea of HeatWatch is to optimize the read reference voltage, i.e., the voltage applied to the cell during a read operation, by adapting it to the dwell time of the workload and the current operating temperature. HeatWatch (1) efficiently tracks flash memory temperature and dwell time online, (2) sends this information to our reliability model to predict the current voltages of flash cells, and (3) predicts the optimal read reference voltage based on the current cell voltages. Our detailed experimental evaluations show that HeatWatch improves flash lifetime by 3.85× over a baseline that uses a fixed read reference voltage, averaged across 28 real storage workload traces, and comes within 0.9% of the lifetime of an ideal read reference voltage selection mechanism.

Failure Analysis (FA) and Design for Testability (DFT) diagnosis play a key role during first silicon bring up, helping identify critical test, design marginality and process issues in a timely and efficient manner. However, as the process technology continues to scale from 28 nm to 10nm FinFET, challenges arisen during FA, as the conventional electrical fault isolation tools reach the limit of optical resolution; while new test strategies are concurrently being introduced. Furthermore, the rising complexity and depth of logic, combined with the high compression ratio of the DFT scan architecture, makes fault diagnostics even more challenging and unreliable. This work will highlight some of the major challenges faced in the introduction of 10nm technology. It includes the intricacies of DFT fault diagnostics and the increasing limitations in electrical fault isolation, as the current available tools reach their minimum detection limits. This paper will present an innovative technique in performing fault isolation in our latest 10nm product to resolve 35% yield loss due to stuck-at-fault (SAF) logic failures during first silicon bring up. The biggest issue faced during debug apart from the fact that the devices were failing across all voltages and frequencies was lack of good diagnostics data that could lead to a viable suspect location. This prompted both DFT and FA teams to work together and develop innovative solutions to arrive to an accurate fault isolation. Lastly, this paper will also present a creative methodology of performing Laser Voltage Imaging (LVI) using scan chain integrity patterns, to debug the functional logic path, when conventional Laser Voltage Probing (LVP) using Automated Test Pattern Generation (ATPG) SAF patterns failed to arrive to a definitive conclusion due to tool resolution limitations.

Fault detection and isolation (FDI) techniques, which are called standard parity space approach (SPSA) and optimal parity vector approach (OPVA), have been presented in literature extensively for engineering sensor systems or sensor networks. This paper demonstrates the abilities of these approaches to detect and isolate outliers in geodetic networks. The ability to detect and isolate outliers has been measured by computing the mean success rate (MSR) for some given probability of significance levels. These approaches have been applied to a levelling network and a Global Navigation Satellite System (GNSS) network. Different matrix decomposition techniques have been used as an alternative way to the Potter algorithm, which is used in SPSA and OPVA. It has been proven that the abilities of FDI techniques, i.e. the MSRs of OPVA, increase with regard to the ones of SPSA in the levelling network and the GNSS network especially if the significance level α is chosen as 0.001 by using Monte–Carlo simulation.

To suppress the error bits of retention-after cycling in 3D NAND flash memory, threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> ) distributions of various program states as well as optimal read voltages are characterized in triple-level-cell (TLC) 3D NAND flash memory. Different from the traditional read-retry strategy by searching for the best read voltages, a simple mathematical model is proposed in this work, aiming at predictions of the optimal read voltage shift (ORVS) with low read latency. The model has been evaluated in various cycling and retention scenarios, showing high prediction precisions. Specially, for blocks with 8k P/E cycles, the prediction accuracy is as high as 96.6% after long-time (335hr@55 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${}^{\circ}\mathrm{C})$</tex> retention.

This work focuses on a broad class of nonlinear process systems subject to control actuator faults and disturbances and proposes a method for data‐based fault detection and isolation that explicitly takes into account the design of the feedback control law. This method allows isolating specific faults in the closed‐loop system; fault detection is done using a purely data‐based approach and fault isolation is achieved using the structure of the closed‐loop system as induced by an appropriately designed controller. This is achieved through the design of nonlinear model‐based state‐feedback control laws that decouple the dependency between certain process state variables in the closed‐loop system. In this sense, the proposed approach constitutes a departure from the available data‐based fault detection and isolation techniques which do not take advantage of the design of the feedback control law to enforce a closed‐loop system structure that enhances fault isolation. The theoretical results are demonstrated through simulations of a CSTR and a gas‐phase polyethylene reactor. © 2007 American Institute of Chemical Engineers AIChE J, 2008

Due to its effectiveness and simplicity, principal components analysis (PCA) has been considered as a basic technique of multivariate statistical process control (MSPC) and it has been applied with a great success in the FDI domain. A set of independent latent variables named principal components (PCs) are created by a linear combination of the original system variables. In the field of sensor fault detection and diagnosis based on PCA, several types of monitoring statistics are well established for enhancing fault detection, where the filtered SPE and SWE statistics are used in this work. After detection, process malfunctions are identified by applying an adequate fault isolation technique. However, various approaches of fault isolation have been suggested in the research literature. The aim of this work is to provide a succinct study exhibiting the ability of three fault isolation methods such as backward elimination sensor identification, contributions charts and fault reconstruction approach to give the correct isolation results via a simulation example.