Abstract
The influence of thinning standard 130-nm CMOS technology device wafers to residual silicon thicknesses of 20 and 5 mum has been studied. Electrical performance was evaluated at wafer level by characterizing various basic device parameters before and after thinning. An increase in the well sheet resistance and a reduction in the gate leakage current were observed. However, both at 25degC and 100degC, no performance degradation was found that could be correlated to the applied thinning techniques, including extreme grinding down to 5 mum. These electrical results are consistent with the experimentally observed submicrometer thinning-induced subsurface damage. Hence, the feasibility of extreme thinning in 3-D integration schemes for standard bulk-Si CMOS was demonstrated.
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