Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects

Abstract

Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of complementary metal–oxide–semiconductor technology. This work presents a comprehensive simulation study on the effects of critical design parameters of 32-nm advanced-process high-kp-channel metal–oxide–semiconductor field-effect transistors on NBTI. The NBTI mechanism and defects were explored for various geometric and process design parameters over a wide range of values. The NBTI simulation method applied in this work follows the on-the-fly method to capture the mechanisms of fast and slow traps. This work illustrates the dependence of the threshold voltage (Vth) degradation on the stress oxide field and stress temperature as well as investigation of the Arrhenius plot for the devices. The temperature insensitivity during short stress time of 1 ms indicates absence of generated defects and presence of preexisting defects. It is also observed that significant defects are generated in the gate stack subsequent to NBTI. The slope obtained from the Vth degradation analysis at 1 ks and 375°C shows that changing the SiO2 interfacial layer thickness affects the Vth degradation by 96.16% more than changing the HfO2 thickness and by 80.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, specifically the boron concentration in the highly doped drain, the metal gate work function, and the halo doping concentration; it was observed that higher boron dose and high metal work function may lead to higher Vth degradation. However, the halo doping concentration in the advanced 32-nm structure has an insignificant effect on NBTI.