Influence of buffer layer engineering in MoS2/CIPS vdW NCFET logic transistor

Abstract

Negative capacitance field-effect transistors (NCFETs) using molybdenum-di-sulphide (MoS2) and copper indium phosphorus sulfide ferroelectric (CIPS) van der Waals (vdW) heterostructure realize energy-efficient electronics due to sharper switching. Adding a buffer layer to the transistor's gate stack boosts the carrier flow. This paper explores various buffer layer candidates that could be used in vdW NCFET. Analysis show Al2O3 and h-BN have superior on/off current ratio in the order of 1012 and enhanced current density in the order of 3 × 105 A/cm2. Notably, Al2O3 exhibits a remarkably low potential of −4.43 V in the channel region, minimizing carrier scattering and consequently enhancing the carrier mobility. The transfer characteristics of Al2O3 demonstrate a low threshold voltage of −1.2 V, a subthreshold swing of 28 mV/decade, and a DIBL of 0.18 mV/V.