Improving the Figure-of-Merit of Integrated Solid-State Diodes through the Use of Nanostructured Porous Silicon

Abstract

Here, we report on the use of nanostructured porous-silicon (PS) technology as an alternative to standard technologies to increase the breakdown voltage VBR of silicon-based integrated solid-state diodes, while leaving the on-state resistance Ron unaltered. Specifically, we show that integration of nanostructured porous silicon in the high-field regions of a standard diode allows a significant increase of the breakdown voltage (VBR > 65 V) to be achieved with respect to a reference diode (VBR = 25 V) under reverse-bias operation. On the other hand, the electrical characteristics of the diode under forward-bias operation are not affected by the presence of nanostructured PS, with Ron changing of only a few percent. If we define as figure-of-merit (FoM) the ratio VBR /Ron , the presence of PS allows the FoM to be improved of a factor of 3. We argue that the nanostructured nature of PS reduces the mean-free path of charge carriers accelerated in high-field regions of the diode reducing, in turn, carrier velocity developed for a given applied voltage under reverse-bias operation.