Abstract
Based on the analysis of typical hybrid-type content addressable memory (CAM) structures, a hybrid-type CAM architecture with lower power consumption and higher stability was proposed. This design changes the connection of a N-type metal-oxide-semiconductor (NMOS) transistor in the control circuit, which greatly reduces the power consumption during comparison by making the match line simply discharge to the NMOS threshold voltage. A comparative study was made between conventional and the proposed hybrid-type CAM architecture by semiconductor manufacturing international corporation (SMIC) 65 nm complementary metal-oxide-semiconductor (CMOS) technology. Simulation shows that the power consumption of the proposed structure is reduced by 23%. Furthermore, the proposed design also adjusts the match line (ML) discharge path. In case that, the not and type (NAND-type) block is matched and the not or type (NOR-type) block is mismatched, the jitter voltage on the match line can be decreased largely.
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