Abstract

The performance of photovoltaic devices is hindered by the presence of barrier height at the interfaces as well as the presence of structural defects. CdTe solar cells, based on a CdS/CdTe heterojunction and CdCl2 vapour treatment, exhibit high efficiency. In this work, we show that the use of a hole-blocking layer has a potential to further increase the efficiency of CdTe-based cells. As a case study, we have fabricated multi-juncton CdTe-based solar cells on both pristine- and textured-silicon substrates. Here we use an n-type zinc tin oxide (ZTO) thin film as the transparent conducting oxide (TCO) layer and an n-type hole-blocking layer of MoO3 on a p-type CdTe:Cu absorber layer. In addition, we map the nanoscale barrier height at each interface, i.e. ZTO/MoO3 and MoO3/CdTe:Cu by Kelvin probe force microscopy (KPFM). We also investigate the real time photo-generated charge carrier dynamics across the heterojunctions using photo-KPFM which plays a major role in the cell efficiency. Quantitative analysis shows that barrier height between the interfaces decreases after light illumination. Based on these findings, we have fabricated solar cells on pristine- and textured-Si substrates and the maximum efficiency is found to be 8.2% for the textured-Si substrate. The present study demonstrates the fabrication of efficient hole-blocking CdTe-based solar cells and provides insights on how local barrier height affects their macroscopic performance.

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