Implications of gate stack scaling in sub-100 nm CMOS speed and reliability

Abstract

Scaling of CMOS devices is projected to continue down to the deep sub-100 nm regime. The gate stack (dielectrics-silicon interface, gate dielectrics and gate contact) is arguably the most critical part of the MOSFET. It is widely believed that oxide will be replaced by high K dielectrics when dielectric thickness is 1.5 nm or below due to excessive direct tunneling (DT) gate leakage. In this work, the effects of high K dielectrics and their interactions with poly depletion (PD), mobility, gate DT leakage and channel charge in sub-100 nm CMOS performance and reliability were investigated.