Abstract
Abstract: The implementation of pipelined multi-precision-based arithmetic operations are carried out. In the existing system, the floating-point operation is based on single precision and is implemented on a divider. The proposed design has been implemented using single, double and quad precision using the universal piece-wise linear (PWL) approximation method and a modified Goldschmidt algorithm. The proposed design performs addition, subtraction, multiplication, and division using the universal PWL method to reduce maximum error. Small multipliers are used in the modified Goldschmidt algorithm. The pipelining process has been used in order to improve the speed of execution and accuracy. This pipelined architecture is described in Verilog and timing performance is measured with Xilinx timing analyser.
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