Implementation of Low-Power High-Speed Clock and Data Recovery

Abstract

The digital clock and data recovery (CDR) circuit during transmission SERDES application was parallel to serial data from one sub-system or systems to another system. Here, the burst of data and clock signals complexity of the system-on-chip (SoCs) has increased in high-speed data communication. Here, no needs to transmit the clock along with the data, if transmit the clock from one system to another system, it increases the noise and reduces the clock quality to avoid that in SERDES application transmit only serial data without a clock and at the receiver end using this serial data using clock data recovery (CDR) mechanisms that generate the clock as well as sample the serial data into same generated CDR clock. The serial data store into the register or FIFO as per our application requirement. In present technologies, the SOC and parallel data transmission at high speeds become a very critical task. To meet with the high processing speeds and enhance system performance, it becomes essential to have SOC high-speed interconnects. Here, CDR with SERDES technology SOC chip and reducing the clock skew as well as reducing the board utilization, in this case like research organizations add additional functionalities and improve the design implementation performance with un-clocked data transmission. Presently, they are widely used in computer networks such as WAN, LAN, and Ethernet, as well as backplane links like PCI express and high-speed telecommunication architectures like SONET and SDH, are among other examples of high-speed serial data links.