Abstract
Hardware implementation is the research focus on improving the processing speed of Hash algorithm. In this paper, through the analysis of the SHA-1 algorithm, the node model of round iteration is designed based on Field programmable gate array (FPGA) and optimized by means of pipelining. Experimental results show that SHA1 algorithm model with three-input adder node achieved good performance, and the maximum throughput of the optimized model reached 138.24 Gbps. The design ideas embodied in papers has universal reference value for the hardware implementation of similar hash algorithm.
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