Abstract
Bias temperature instability (among other problems) is a key reliability issue with nanoscale CMOS transistors. Especially in sensitive circuits such as sense amplifiers of SRAM arrays, transistor aging may significantly increase the probability of failure. By analyzing the Current Based Sense Amplifier circuit and Voltage-Latched Sense Amplifier circuit through HSPICE simulations, we observe that under the effects of Negative Bias Temperature Instability (NBTI) aging alone, the failure probability increases for both circuits. However, under Positive Bias Temperature Instability (PBTI) only or the combined effects of both NBTI and PBTI, failure probability reduces over time.
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