Impact of physical and electrical thickness scaling on the reliability of plasma-nitrided gate dielectrics in a 90 nm SOI manufacturing technology

Abstract

Appropriate balancing of the polysilicon dopant concentration and the physical gate dielectric thickness is required so as to accomplish a minimized capacitance equivalent thickness (CET) at low gate leakage ( J G) and high reliability. Here, we investigate the impact of polysilicon predoping and physical gate-dielectric thickness scaling on the interaction of CET, J G and TDDB reliability for both NMOS- and PMOS-devices for physical thicknesses between 1.28 and 1.58 nm. Furthermore, the impact of an additional N 14 + ion implantation into the PMOS gate is investigated. For NMOS both modal lifetime and leakage current density are not influenced by changes of the poly-depletion layer thickness or the CET, respectively, that result from increasing phosphorus implant dose. Since J G scales with physical thickness and since modal lifetime strongly depends upon J G, both physical thickness and leakage current density can be used to determine the thickness scaling of gate dielectrics reliability. A similar result is found for pMOS though the CET is varied less by the increased boron doping level. Boron penetration resulting in degraded TDDB reliability was observed for the physically thinnest split for excess boron doping by p-polysilicon ion-implantation. An additional nitrogen implant into the p-poly proved to prevent pMOS devices from reliability degradation, however, at the expense of any scalability margin that additional boron would eventually offer.