Impact of Gate Oxide Traps and In0:53Ga0:47As/BOX traps on the Performance of In0:53Ga0:47As on insulator TFET and its Mitigation

Abstract

In this paper, we present the impact of gate oxide and back-side interface (In 0.53 Ga 0.47 As/BOX) traps on the performance of In 0.53 Ga 0.47 As on insulator TFET. It is revealed through 2D-TCAD analysis that along with gate oxide traps, traps at back-side interface can significantly alter the performance of In 0.53 Ga 0.47 As on insulator TFET. The presence of In 0.53 Ga 0.47 As/BOX traps alone can increase the OFF current ~ 22 times, and cumulative effect of the presence of traps at gate oxide interface and In 0.53 Ga 0.47 As/BOX interface is an increase in OFF current by ~ 3 order of magnitude, thus deteriorating the ON=OFF current ratio significantly. We also propose the methodologies to mitigate the effect of traps in OFF state. By mitigating the decrease in flat band voltage caused by presence of traps, through p type doping of channel instead of n-type channel and using the graded doping in the source, the OFF current is reduced in trap affected TFET. The application of proposed methodology in trap affected TFET offers > 3 order reduction in OFF current, thus restoring the ON=OFF current of In 0.53 Ga 0.47 As TFET. The proposed methodology provides the ON=OFF of 1.41 × 10−5A=_m