Abstract
In the past, the large area of heterojunction bipolar transistors (HBTs) in silicon germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) processes has prevented them from being widely used in ultrahigh-speed digital systems. The consequent longer interconnects among HBTs also offset the speed advantage of HBTs. In this brief, four deep trench isolation sharing (DTIS) methods are proposed to significantly reduce the HBT layout area. The 2 × 2 HBT layout area can be reduced by 20%-42%, and large-scale HBT system layouts can be reduced by 24%-48% or even further. Two IBM 0.18- mum SiGe 7HP chips based on Xilinx 6200 digital configurable logic blocks (CLBs) and logic cells were fabricated for verification. The maximum difference between measurement and postlayout simulation is 6.1%. Compared with the traditional layout implementation, the DTIS layout improved the system speed by 22% due to shorter interconnects among HBTs.
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