Abstract
The authors discuss the design of SC (switched-capacitor) decimators whose transfer functions have infinite impulse response (IIR). Novel optimum architectures are developed for which the speed requirements of the amplifiers are determined by the lower sampling rate, thus rendering the circuits particularly attractive for high-frequency applications. Appropriate Z-transfer functions are derived for first- and second-order IIR SC decimator building blocks. Design examples of optimum IIR SC decimators with different types of frequency response, as well as different factors of sampling rate reduction, are presented to demonstrate their practical feasibility.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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