Identification of spatial localization and energetic position of electrically active defects in amorphous high-k dielectrics for advanced devices

Abstract

In this work, we report the use of the conductance transient technique (GTT) to evaluate disordered-induced gap states (DIGS) in gate dielectrics of metal-insulator–semiconductor (MIS) structures. These states are electrically active defects inside the dielectric bulk which are preferentially located at regions near the dielectric/semiconductor interface. Conductance transients occur when the MIS structure is driven from deep to weak inversion, at various frequencies and temperatures, allowing us to obtain contour line maps of defects spatially and energetically distributed inside the dielectric. This method has been applied to evaluate DIGS densities in advanced high-k gate dielectrics, such as HfO2, Al2O3, TiO2, silicates and other mixtures grown on silicon substrates by atomic layer deposition under different process conditions. Commonly, high DIGS densities involve low interface state densities Dit and vice versa, indicating that there is some kind of interaction or evolution between these two types of defects or traps. An explanation for the dynamics dictating the transformation of interface states to DIGS states is a key point in determining the quality of the dielectric films.