Hybrid on-chip interconnection with coupled cores in tiles

Abstract

More and more cores are integrated onto a single chip to improve the performance of processors and reduce the power consumed by computing. The interconnection of the cores is a new issue for high performance. Network-on-Chip (NoC) is proposed as the promising paradigm for this problem. Because there are many cores on chip, different on-chip interconnection structures have been proposed. Hybrid interconnection with bus and on-chip network has been proved as efficient design. However, current works focus on the structure design only without taking the tasks into account. In this paper, we first analyze the communication model of the tasks. And then a novel on-chip interconnection architecture is proposed. In this new structure, cores are divided into different tiles. In the same tile, the cores are connected by bus and different tiles are interconnected by on-chip network. Experimental results show that most communication between the tasks is limited into tiles and the hybrid interconnection architecture can reduce the communication on-chip. It also outperforms the MESH architecture of NoC.