Hybrid Integration in 3D NoC with Efficient Path Establishment Mechanism in Circuit Switching

Abstract

On chip communication is now an upcoming technology; whereOn-chip interconnections are becoming tedious as they need to assure reliability, power, speed and scalability issues. Systems on chips, (SoCs), are so intricate that they oblige new interconnection techniques. Networks on Chip (NoCs) have paved way to resolve these problems. As application is becoming complex they require good design for greater bandwidth and performance which lead to 3D NoC. 3D NoC provide best solutions to connect as many functional elements on-chip over 2D NoC. Data flow NoCs can be categorized into: packet switched and circuit switched NoCs. The paper focus on simultaneous circuit and packet switching to benefit from two methods which ensures low latency and more resource utilization. Here in this paper, the circuit switched NoC is much concentrated where we implement our ideas in area like circuit setup method. Here we bring in a new method for guaranteed Quality of Service (QoS) known an efficient path establishment mechanism in circuit switching in 3D Torus topology. Torus topology aims to produce less latency of other topologies, where the path is estimated based on to the destination node layers and position. This paper is more advantageous where it can get switched between to different layers and position in which destination is placed. As of 3D NoC with increased number of nodes it ensureslow power, low latency, increase hardware integration, improved throughput and enables multi core processing and also resolves scalability crisis. It can operate on both packet and circuit switching which reduces both cost and operational expenses. Analysis on latency, power and throughput is made for 3D hybrid integration which provides better solutions. Optic Communication can be extended for future progress for improved speed and accuracy.