Hybrid, adaptive, and reconfigurable fault tolerance

Abstract

The main design challenge in developing space computers featuring hybrid system-on-chip (SoC) devices is determining the optimal combination of size, weight, power, cost, performance, and reliability for the target mission, while addressing the complexity associated with combining fixed and reconfigurable logic. This paper focuses upon fault-tolerant computing with adaptive hardware redundancy in fixed and reconfigurable logic, with the goal of providing and evaluating tradeoffs in system reliability, performance, and resource utilization. Our research targets the hybrid Xilinx Zynq SoC as the primary computational device on a flight computer. Typically, flight software on a Zynq runs on the ARM cores that by default operate in symmetric multiprocessing (SMP) mode. However, radiation tests have shown this mode can leave the system prone to upsets. To address this limitation, we present a new framework (HARFT: hybrid adaptive reconfigurable fault tolerance) that enables switching between three operating modes: (1) ARM cores running together in SMP mode; (2) ARM cores running independently in asymmetric multiprocessing (AMP) mode; and (3) an FPGA-enhanced mode for fault tolerance. While SMP is the default mode, AMP mode may be used for fault-tolerant and real-time extensions. Additionally, the FPGA-enhanced mode uses partially reconfigurable regions to vary the level of redundancy and include application- and environment-specific techniques for fault mitigation and application acceleration.