High-Performance On-Chip Low-Pass Filters Using CPW and Slow-Wave-CPW Transmission Lines on Porous Silicon

Abstract

We report on the design, fabrication, and characterization of high-performance stepped-impedance filters (SIFs) on a locally formed porous Si layer on the CMOS Si wafer. This technology provides the appropriate platform to reduce the high losses within the Si substrate, along with the possibility to tune the substrate permittivity in order to achieve high characteristic impedance ( $Z_{C}$ ) transmission lines, which are important for the specific filters and other passive circuits, e.g., power dividers. By combining high- $Z_{C}$ coplanar waveguides (CPWs) and low- $Z_{C}$ slow-wave CPWs (S-CPWs), high-quality SIFs were achieved, with cutoff frequencies at 30 and 60 GHz. These SIFs were characterized in the frequency range of 0–100 GHz and demonstrated an insertion loss lower than 2 dB in the whole passband and a rejection higher than 30 dB in the stopband. The achieved performance is better than that exhibited by SIFs using only S-CPWs.