High-performance devices in the new century: optical lithography and mask strategy for 0.13-μm SoC (Photomask Japan 2000 panel discussion review)

Abstract

In the Photomask Japan Symposium this year, a Panel Discussion was held on the optical lithography and mask strategy for 0. 13-um system on a chip (SoC) on April 13, 2000 at Yokohama. Major concerns are device process and business impact on mask and litho requirements, realistic mask specifications to meet such business, optical lithography technology strategy, the status of optical exposure tool development and mask with tighter specs. Then the most important issue for device, litho, exposure tools and masks are summarized. For lithography, layer by layer optimization of masks and illumination, smaller mask error enhancement factor (MEEF), phase-shifting mask (PSM) design integration to match existing layout rules and ArF exposure tool costs are the major tasks. For masks, quick mask delivery, 10-nm critical dimension (CD) control and optical proximity effect correction (OPC) pattern fidelity are the major ones.