High-Density Compliant Die-Package Interconnects

Abstract

Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package substrate; and (2) the die-to-package interconnection, i.e. the bump, transmits the CTE-induced mismatch stresses directly to the ILD (Chandran et al., 2004). Compliant die-package interconnects (Zhu et al., 2004) substituted for conventional C4 flip-chip interconnections promises to offer reduction in package induced stresses onto the silicon die consisting of low-k ILD layers. The reduction of stresses achieved with these compliant interconnects is by decoupling the die and the package substrate such that either entity is able to deform without constraining the other. Extensive thermomechanical simulation using various modeling approaches predicts an ILD stress reduction offered by compliant interconnects to be between 17-57% relative to conventional C4 flip-chip bump. A prototype compliant interconnect structure was fabricated on a low-k ILD silicon test-chip with 180/spl mu/m C4 pitch and packaged onto an organic substrate with Pb-free solder. Assembly end-of-line (EOL) data was collected to assess the ILD stress reduction, warpage analysis, I/sub max/ and electromigration performance of the compliant interconnects. The focus of this paper is a comparison of the performance of compliant die-package interconnects as a substitute for conventional C4 flip-chip bump technologies in low-k ILD architectures.