High throughput hardware architectures for asymmetric numeral systems entropy coding

Abstract

In this paper two new hardware-based entropy coding architectures for asymmetric numeral systems are introduced, as entropy encoding is one of the major phases in a compression algorithm. The proposed architectures are based on tabled asymmetric numeral systems (tANS). The tabled asymmetric numeral systems combines the speed advantage of table based approaches (e.g. Huffman encoding) with the higher compression rate advantage of arithmetic encoding. Both proposed architectures have been synthesized to a state-of-the-art FPGA, and the synthesis results show high encoding throughput. The architectures are capable of encoding one symbol per clock cycle. The performance of the architectures depends on the number of symbols in the alphabet and may vary from 146 up to 290 Mega symbols per second (Msps).