High-throughput and area-efficient fully-pipelined hashing cores using BRAM in FPGA

Abstract

In this paper, an area-efficient fully-pipelined architecture of SHA-1 and SHA-256 implemented on FPGA is proposed for achieving high operating frequency and throughput. The conventional pipeline architecture consumes a lot of registers, especially the consumption increases dramatically for the higher number of pipeline stage. To solve this problem, a new scheme using block RAM (BRAM) is presented to reduce consumption of registers and make the fully-pipelined architecture simpler. Additionally, to achieve operating frequency greater than 300 MHz, the new sub-cores of SHA-1 and SHA-256 combined with the loop unrolling and pre-computation techniques are introduced to the design. Compared to previous works, the throughput and throughput/Slice of SHA-1 and SHA-256 in proposed designs are substantially increased to 159.590 Gbps, 16.083 Mbps/slice and 154.880 Gbps, 10.94 Mbps/slice respectively on Kintex-7 FPGA.