Abstract
In this brief, new architectures are presented for the conversion of residues to binary equivalents in the (2n-1, 2n, 2n+1) moduli set. Both of the architectures presented are based on a new algorithm, which eliminates a multiplication. In the design of the architectures, speed and cost are considered as the principal factors. The proposed architectures use fewer multipliers and adders of smaller size. A comparison in terms of hardware requirements, delay estimates, and complexity is made to establish the advantages of the proposed design.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
