Abstract
A mix-signal high precision capacitor mismatch error calibration method for charge domain pipelined ADCs is proposed. The calibration method calibrates the capacitors one by one based on binary search. Charge errors caused by the capacitor mismatch in and between pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed calibration method, a 14bit 250MS/s charge domain pipelined Analog-to-digital converter (ADC) is designed and realized in a 1P6M 0.18 m CMOS process. Test results show the 14bit 250MS/s ADC achieves the signal-to-noise ratio of 70.7dBFS and the spurious free dynamic range of 84.6dB, with 70.1MHz single-tone sine wave input at 250MS/s, while the ADC core consumes the power consumption of 235mW and occupies an area of 3.2mm 2 .
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