High-Performance Reconfigurable Architecture for Lightweight Block Ciphers

Abstract

Aiming at the problem that the current hardware implementation architecture using ASIC is difficult to meet the flexibility requirements of different applications, a high-performance reconfigurable architecture for lightweight block cipher (HRALBC) is proposed. By analyzing 42 mainstream lightweight block cipher algorithms, the pattern features and combination features of the algorithm are extracted; The reconfigurable processing unit is designed based on the pattern feature results and combined feature results; The reconfigurable processing unit array is designed according to the algorithm mapping law, and then the overall architecture is designed. Map different types of algorithms to HRALBC, verify their functional correctness, and analyze the mapping results. The experimental results show that under TSMC 55 nm CMOS process, the working frequency of HRALBC can reach 429 MHz, and the total area is 1.23M equivalent gate (GE). For different cryptographic algorithms, the area efficiency can be up to 22.33 Gbit·s^-1·MGE^-1. Compared with the Anole, for PRESENT64/80, SPECK64/128 and SIMON64/128 algorithms, the utilization of reconfigurable units is increased by 16.67%, 16.67% and 13.89% respectively, and the area efficiency is increased by 66.64%, 66.64% and 11.04% respectively.