Abstract
Development of high-level synthesis tools such as OpenCL SDK for FPGAs enables us to design accelerators for scientific applications that can take advantage of flexibility and efficiency of FPGAs. However, the available OpenCL SDKs only support the standard floating-point (FP) formats. In this paper, we present the performance evaluation of high precision FP operations, which are currently not supported in OpenCL, on recent FPGAs. By using a mechanism to call a custom design from an OpenCL kernel, we evaluate the performance of a sample application in high precision FP format binary128. We found that the sustained performance of our design in binary128 on Intel Arria10 and Stratix10 is 19 and 71 Gflops, respectively.
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