Abstract
Problem statement: In any multimedia processor, controller may consume most of the on- chip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software r eference implementation. The whole system is implemented in 0.18 µm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% d uty cycle correction. Results: From the measurement result of DLL operation, the output clo ck jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.
Highlights
MATERIALS AND METHODSIn recent years, the performance is the most important in real time image and video applications
The memory interface used to operate in the active state, where the signals are all active mode of operation
A prototype circuit is designed in 0.18 μm technology, duty cycle error reduces to 0.8% which makes good stability, fast-responsive
Summary
The performance is the most important in real time image and video applications. Power and ground distribution for high-speed systems becomes critical (Oklobdzija, 2003) In these high performance systems, Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are usually used to generate the clock signal which is required to implement clock deskewing circuit in RF transceiver, inter-chip communication interfaces and clock distribution. Variations in this timing reference (i.e., clock jitter) require designs to incorporate additional margins that degrade performance and can cause bit errors in communications systems.
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