High level synthesis - reconfigurable hardware implementation of programmable logic controller

Abstract

The paper presents implementation of PLC (hardware and software part) with use of reconfigurable logic devices (based on FPGAs). Different framework architectures that accommodate user requirements are presented. There is widely discussed synthesis process of control algorithm given by LAD. The synthesis process is targeted for hardware implementation in FPGA structure. Different optimization aspects and architecture optimal fitting are presented. Finally benchmarks compare logic requirements for controller and its performance in comparison to standard industrial solution.