High-Frequency and Sensing Performance Optimization of Black Phosphorus Channel InSb/InGaAs TFETs: A Dual-Function RF Stability and Biosensing Perspective

This work investigates the impact of dielectric halo doping on the radio-frequency (RF) and analog characteristics of InSb/InGaAs tunnel field-effect transistors (TFETs) with a black phosphorus (BP) channel. Source-side dielectric halo doping significantly reduces ambipolar conduction, especially when the negative gate bias is strong. The study evaluates how TiO2-high-k and SiC-low-k dielectric halo materials affect important analog and radio frequency parameters, including gate-to-source capacitance, transconductance, output resistance, gain-bandwidth product, and cut-off frequency, using comprehensive TCAD 3D simulations with Silvaco. The results demonstrate that while high-k halo doping effectively lessens ambipolar effects, low-k materials enhance analog and radio frequency performance. Furthermore, a comparison of transient behaviour shows that the BP-channel InSb/InGaAs TFET performs better than conventional TFET designs, making it a viable option for high-frequency and energy-efficient circuit applications.

In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut‐off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability.

In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Analog/RF performance of four different Tunneling FETs with the recessed channels

We have proposed a tunneling field-effect transistor (TFET) having a GaAs/InGaAs heterojunction structure for radio frequency (RF) application. The GaAs/InGaAs heterojunction TFETs are investigated in terms of DC and RF characteristics by using the device simulation technology. The proposed TFET showed excellent subthreshold swing (S) and on/off current ratio as low standby power (LSTP) devices. Moreover, the superb RF performances of proposed TFET were obtained by designing drain doping (DDrain). It was confirmed that the GaAs/InGaAs heterojunction TFET is suitable for RF applications.

Black phosphorus (BP) has recently emerged as a promising semiconducting two-dimensional material. However, its viability is threatened by its instability in ambient conditions and by the significant decrease of its band gap in multilayers. We show that one could solve all the aforementioned problems by interfacing BP with hexagonal boron nitride (hBN). To this end, we simulate large, rotated hBN/BP interfaces using linear-scaling density functional theory. We predict that hBN-encapsulation preserves the main electronic properties of the BP monolayer, while hBN spacers can be used to counteract the band gap reduction in stacked BP. Finally, we propose a model for a tunneling field effect transistor (TFET) based on hBN-spaced BP bilayers. Such BP TFETs would sustain both low-power and fast-switching operations, including negative differential resistance behavior with peak-to-valley ratios of the same order of magnitude as those encountered in transition metal dichalcogenide TFETs.

Black phosphorus (BP) is one of layered materials drawing significant attentions in solid-state and electrochemical societies. BP has a direct bandgap, which can be tuned by varying the thickness of material or the number of layers. Due to its large carrier mobility, BP is considered as a promising contender for the future electronic device applications. However, designing field-effect transistors (FETs) based on BP is not straightforward since the relevant device physics can be significantly different from that of conventional metal-oxide-semiconductor (MOS) FETs based on 3D materials such as silicon or III-V semiconductors. Therefore, careful engineering practices are required to use BP for transistor applications. In this study, we will mainly discuss design strategies for conventional FET structures and tunnel FETs (TFETs) based on the novel layered material of BP. We perform self-consistent atomistic quantum transport simulations using non-equilibrium Green’s function (NEGF) formalism with tight-binding approximation. For high-performance device applications, conventional FET structure based on BP is considered. Our simulation results reveal that, among few-layer BPs, monolayer BP can provide the best device performance with the largest on current (~5 mA/μm), the largest on-off current ratio (~107), and the smallest subthreshold swing (62 mV/dec), showing three times larger on current and three orders of magnitude smaller off current compared to 2022 International Technology Roadmap for Semiconductors (ITRS). Although bilayer BP FETs also exhibit as comparable device performance as monolayer BP FETs, in general, thicker BP is not preferable mainly due to the worse gate electrostatic control, which affects the overall device performance negatively. Secondly, for low-power devices, BP is integrated into the lateral tunnel FET structure, where small off current and steep subthreshold slope are of great importance rather than on state characteristics. Our simulation results show bilayer and trilayer BP are preferable for TFETs applications, unlike the conventional FET structure, while monolayer BP suffers from small on current due to its large bandgap. By carefully engineering various device parameters, an ultra-high on-off current ratio (> 1011) and an extremely small subthreshold swing (~15 mV/dec) can be achieved in bilayer and trilayer BP TFETs, demonstrating the great potential of few-layer BP over monolayer. This study shows that BP FETs can be tuned for various target applications by engineering the material and device parameters properly.

This paper presents the impact of parameter fluctuation due to process variation on radio frequency (RF) stability performance of double gate tunnel FET (DG TFET). The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit (FoM) such as cut-off frequency (ft), maximum oscillation frequency (fmax) along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines of DG TFET for RF applications.

A comparative study has been carried out on the performance parameters of P-Channel Tunnel Field Effect Transistors (TFETs) using Graphene Nanoribbon (GNR) as channel material with those using Si, Ge, InAs, and InSb. The purpose of this paper is to find out the appropriate channel material of TFETs to achieve low-power and high performance for digital application. The energy band diagram of the device is obtained from the numerical solution of 1D Poisson equation subject to appropriate boundary conditions. An indigenously developed simulation software based on a self-consistent iterative method has been used for this purpose. The surface potential at the interface of gate dielectric and channel as well as barrier height are extracted from the energy band diagram. The drain current is calculated from the energy dependent tunneling probability and Fermi functions at the source and drain regions. It is observed that p+ TFETs with GNR as channel material provides higher on–off current ratio, better gate capacitance and lower intrinsic gate delay as compared to those with other channel materials.

Tunnel Field Effect Transistor (TFET) is gaining recognition and provide solution for Integrated Circuit (IC) design with low power. This is due to TFET's carrier transportation scheme, which utilizes inter-band tunneling of carriers, and its fabrication similarity to MOSFET. TFET presents itself as a widely adopted device structure that can overcome the limitations of MOSFETs. However, TFETs suffer from poor DC and Radio Frequency (RF) performance, mainlydue to minority carrier transport and physical doping, which forms an abrupt junction in nanoscale devices due to RDFs. The junction-less device structure presents a viable solution to these issues without sacrificing DC parameters, even at high-frequency. Furthermore, the nanotube structure of TFET effectively reduces the Subthreshold Swing (SS) and leakage current due to better controllability of channel. The gate-all-around structure of nanotube TFET improves the surface potential distribution over the channel region, not only enhancing the DC characteristics of TFET but also improving the high-frequency parameters. The core gate Nano Tube (NT)-TFET is a promising device structure for exploring its application in the field of biomedical science as a biosensor. The proposed core gate nanotube structure provides a larger surface area for immobilizing biomolecules in the cavity, thus improving sensitivity analysis. This work proposes the utility of a novel core gate NT-TFET as a biosensor for detecting label-free biomolecules and DNAs. In this design, the detection capability of biosensor is improved, and the detection processes are investigated by high-frequency parameters of the proposed twin cavity dual metal NT-TFET biosensor. This study demonstrates the sensitivity analysis of biosensor based on transit time and device efficiency, which are two critical high-frequency parameters. This approach results in a biosensor with a lower annealing budget, making it more cost-effective and with comparatively highersensitivity

Design rules of the conventional MOSFETs are continuously decreasing, along with the strong requirement of extremely low subthreshold swing level of more than 50 mV/dec at a sub-6-nm node1. As the MOSFET devices cannot meet the demands of key markets, such outstanding electrical features: low-power, high on/off ratio, low off-current, and high on-current, a quantum tunnel FET(TFET) have garnered considerable interest as a crucial alternative to overcome the above issues. However, The TFET has the disadvantages of introducing random dopants fluctuation(RDF) event initially caused by carrier diffusion in the channel region2. Thus, doping-less(DL)-TFET approach using a charge-plasma concept has become highly promising option for use in future TET research areas3,4. In this work, we address a novel device structure and practical fabrication procedure for the sub-10-nm TFET ensuring advanced am-bipolar and ON-state current behaviors on the basis of the well-known charge plasma concept.We experimentally fabricated and analyzed the conventional DL TFET (see Fig. 1(a)). The roughness of the gate oxide and the interface was high. (see Fig. 1(b)) As a result, the DL TFET showed relatively high am-bipolar and low ON-state current characteristics, as shown in Fig. 1(c). The proposed device includes a 3-nm-thick compact-drain(CD) for the efficient suppression of am-bipolar current and hetero-material(HM) of Si(drain)-SiGe(channel)-Ge(source) for the improved ON-state current, where a particular Ge-condensation process developed in our previous work is adapted for the formation of HM. The CD-HM-DL TFET starts with a thin SOI wafer and fin-type structure to facilitate the fabrication process, as seen in Fig. 1(d) and (e). The TCAD simulation findings imply that a silicon band-gap is highly dependent on the drain thickness owing to a quantum size effect and the band-gap energy is found to be a 1.27 eV at about 3-nm-thick silicon. In addition, the am-bipolar current of the 3-nm-thick CD-DL TFET provides an extremely low current (more than 160 times), when compared with that of a conventional doping-less(DL) TFET with 10-nm-thick drain, as displayed in Fig. 1(f). The HM-DL TFET based on the Si(drain)-SiGe(channel)-Ge(source) configuration exhibited a tunnel path of 2.1 nm at a gate voltage 1.5 V, which is 44.7 % lower than the conventional DL-TFET. The ON-state current of the HM-DL-TFET is 4.8 times higher than that of the conventional DL-TFET, as seen Fig. 1(g). When the compact Si-drain, SiGe-channel and Ge- source were applied, in particular, am-bipolar and ON-state characteristics were improved, as evident in Fig. 1(h). The results indicate that the proposed CD-HM-DL TFET may establish a useful and simple route for advanced electrical performance, such as suppressed am-bipolar current and increased ON-state current, which is possibly essential to the realization of low power and high performance applications by using a relatively small number of few fabrication steps. Figure caption Fig. 1. The conventional DL TFET and proposed CD-HM-DL TFET configuration and electrical characteristics (a) DL TFET schematics, (b) TEM Cross-sectional image, (c) I-V curve of DL TFET, (d) CD-HM-DL TFET schematics, (e) The AA’-line cross-sectional view, (f) band-gap energy with Si-thickness and I-V comparison of DL TFET with 3-nm-thick CD TFET (g) I-V comparison of DL TFET with Si(drain)-SiGe(channel)-Ge(source) HM TFET and (h) I-V comparison of DL TFET with CD-HM-DL TFET References J. Ahopelto, G. Ardila, L. Baldi, F. Balestra, D. Belot, G. Fagas, S. De Gendt, D. Demarchi, M. Fernandez-Bolaños, D. Holden, A.M. Ionescu, G. Meneghesso, A. Mocuta, M. Pfeffer, R.M. Popp, E. Sangiorgi, C.M. Sotomayor Torres, Solid State Electronics, vol. 155, pp 7-19, May 2019. doi: 10.1016/j.sse.2019.03.014.M.H. Chiang, J.N. Lin, K. Kim, C.T. Chuang, IEEE Transactions on Electron Devices, vol 54, No. 8, pp. 2055-2060, Aug 2007. doi: 10.1109/TED.2007.901154 R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, IEEE electron device letters, vol. 29 No. 12, pp. 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 4. M.J. Kumar, S. Janardhanan, IEEE Transactions on Electron Devices, vol 60, No. 10, pp. 3285-3290, Oct 2013. doi: 10.1109/TED.2013.2276888 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

RF stability performance of SOI junctionless FinFET and impact of process variation

In this paper, five layered Black Phosphorus (BP) – Silicon (Si) based Tunnel Field Effect Transistor (TFET) is used to overcome the thermionic limits faced by Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and analysis of the device validates that TFET is a better alternative as nano scale transistor. To enhance the ON state current for five layered BP-Si based TFET, multi electrode (source and drain) based structure is used. For the first time, the charge plasma technique is implemented on BP. The proper work function of metal electrodes has been selected to accordingly implement the charge plasma based technique for BP and Si. Charge plasma will result in generation of electron and hole cloud depending on the work functions at source/drain electrode. Different device properties and characteristics curves viz. IDS-VGS and IDS-VDS are compared for monolayered TFET to five layered based TFET. Different analog/RF properties, as well as linear and distortion parameters of the device such as output conductance (gd), transconductance (gm), cut-off frequency (fT), third order intermodulation distortion, second and third order harmonic distortion, second and third order voltage intercept point and current intercept point, are examined for five layered BP-Si based TFET only. For five layered BP-Si based configuration, the proposed device offers a threshold voltage of 0.42 V, an average subthreshold slope of 24.14 mV/dec, ION of 1.7 × 10−4 A/μm, Drain Induced Barrier Lowering (DIBL) of 1.02 mV/V.

Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells

This paper investigates the RF Stability performance of the Double Gate Junctionless Tunnel Field Effect Transistor (DGJL-TFET). The impact of the geometrical parameter, material and bias conditions on the key figure of merit (FoM) like Transconductance (gm), Gate capacitance (Cgg) and RF parameters like Stern Stability Factor (K), Critical Frequency (fk) are investigated. The analytical model provides the relation between fk and small signal parameters which provide guidelines for optimizing the device parameter. The results show improvement in ON current, gm, ft and fk for the optimized device structure. The optimized device parameters provide guidelines to operate DGJL-TFET for RF applications.