Hierarchical LUT structures for leakage power reduction (abstract only)

Abstract

Reconfigurable technologies have made remarkable progress in the last few years. However, due to the overhead of programmability along with improved system capabilities, power dissipation has become one of the major concerns for designers. Moreover, with the trends in technology scaling, overall leakage power consumption is increasing alarmingly. In this work, we propose a leakage power optimization technique using look-up tables (LUTs) for SRAM-based FPGAs. Analysis of a set of 20 MCNC benchmarks using 4-input LUTs show that on an average only 53% of these LUTs use all their inputs. Based on this observation, we shut down SRAM cells and certain transistors associated with the unused inputs by employing hierarchical look-up tables, which can yield LUTs with varying number of inputs within the same logic block. We effectively utilize a Vdd gating scheme to cut-off power supply to one half or three quarters of the original 4-input LUT, which in turn yields a 3-input LUT or a 2-input LUT from a 4-input LUT respectively. Our experiments show that for 180 nm technology logic block leakage power savings is 22.9% on an average for the set of 20 MCNC benchmarks. This saving will be even higher for technologies 90 nm and smaller.