Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems

Abstract

As the technology is advancing day by day, the need of high performance devices is also increasing. High performance is achieved at the expense of high power dissipation. Nowadays, field programmable gate arrays (FPGAs) are widely used in wireless communication systems due to their low non-recurring cost and high operating speed. There are many high performance applications (i.e., image processing, digital signal processing, wireless transceivers etc.) in which FPGAs are widely used. However, their complex architectures lead to high power consumption. Estimation of power in the early stage of the design flow would help designers to design the systems as per specified power budget. Therefore, two different approaches for power estimation are proposed in this paper. First is the heuristic approach based on back propagation neural network and second is the regression based statistical approach. It is observed that heuristic approach is better as compared regression in terms of power estimation of most of the digital circuits considered in this work.