Abstract
To overcome various concerns caused by scaling-down the device size in future LSIs, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of device chips with different size, different devices and different materials are vertically stacked. To achieve such heterogeneous 3D integration, a key technology of self-assembly and electrostatic (SAE) bonding has been developed. Exploring new devices for the IoT, we have fabricated several kinds of heterogeneous 3D LSIs called super-chip by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips using SAE bonding.
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