HDL driven chip layout within the FHDL design framework

C.D Morency,Z Wang,P.M Maurer

doi:10.1109/secon.1990.117851

HDL driven chip layout within the FHDL design framework

C.D Morency, Z Wang + Show 1 more

https://doi.org/10.1109/secon.1990.117851

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Publication Date: Apr 1, 1990

Citations: 12

Affiliation: University of South Florida

#Programmable Logic Arrays #Read-only Memories + Show 8 more

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Abstract

Techniques of automatically generating layout from Florida Hardware Design Language (FHDL) specifications are presented. These techniques allow for the automated layout of read-only memories (ROMs) and programmable logic arrays (PLAs), and they allow for the user-assisted automatic layout of standard-cell blocks. Adaptations of the FHDL and its framework to permit layout synthesis are presented. Cell generation is discussed. Adapting the simulation framework and primitive simulation modelling are discussed. >

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