Abstract
True motion estimation is a well-known technique to find the true object motion trajectory in a video, and it has a lot of applications in computer vision and display systems. However, if the target frame size becomes large, many new design challenges are introduced, such as huge computation, large bandwidth and large on-chip SRAM size requirements. Within the consideration of both algorithm and architecture, we develop a true motion estimator with ±128x±128 search range for video systems with Full-HD (1920×1080) resolution. The PSNR evaluation shows that our algorithm is better than other three existing algorithms. For hardware implementation, we use Verilog-HDL and synthesize it by SYNOPSIS Design Compiler with UMC 90nm cell library. The implementation works at 300MHz frequency, and it shows that there are total 76% bandwidth reduction, 66% cycle reduction and 88% on-chip SRAM reduction with the proposed ping-pong two-way scheduling and motion vector grouping techniques.
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