Hardware Trojan detection by timing measurement: Theory and implementation

Abstract

Due to outsourcing of chip product chain, hardware is vulnerable to be attacked. For example, an attacker who has access to hardware fabrication process can alter the genuine hardware with insertion of concealed hardware elements (Hardware Trojan). Microelectronic circuits are almost always a part of hardware devices, so microelectronic circuit Hardware Trojan (HT) detection becomes a key aspect in hardware security. A novel microelectronic HT detection circuit based on timing analysis is proposed in this paper. The detection circuit can be adopted in combinational and sequential microelectronic circuits. The proposed technique is implemented in IBM 90 nm CMOS process and Xilinx ISE FPGA. Based on experimental results, with one detection circuit embedded in testing-path, an HT with size that is 2.81% of host-circuit size is detectable at detection probability of 90% with a 10% probability of a false positives. Both detectable HT size and detection probability can be improved by adding more detection circuits to testing-path. The probability of false positives is controlled by the testing clock period.